In CAD design environments the need may arise of porting a previously developed design from a technology platform to another one.
The increasing complexity of designs as experienced e.g. in the area of microelectronics (for instance in designing Integrated Circuits or ICs) may make this operation rather complex due to the current unavailability of Electronic Design Automation (EDA or EGAD) tools adapted to perform a porting operation in an automatic way while maintaining design kit references.
For instance, certain porting tools available from Sagantec North America of 2075 De La Cruz Blvd, Suite #105, Santa Clara, Calif. 95050 work at the shape level and act only on elementary layout structures (e.g. rectangles, paths, polygons), thus failing to preserve all connections to the reference design kit objects.
U.S. Pat. No. 6,088,518 to Hsu, which is incorporated by reference, discloses a method and system for porting an integrated circuit layout from a reference process to a target process by placing components related to the reference process on a grid determined by equations that are based upon the desired layout architecture. The design rules of the target process are used along with the equations to determine the grid of the target process. The component layout is controlled by parameters, where the design rules provide the values of the parameters so that each component is ported when the parameter values are changed to that of the target process. The locations of the components are eventually mapped grid-point to grid-point from the reference process to the target process, so that an integrated circuit layout in the target process is drawn without design rule violation.
The arrangement of Hsu is applicable to a layout structure only, and operates at the level of (geometrical) shapes and thus needs technological data to re-design the device being migrated.
Also, Hsu fails to provide any links to design libraries and does not refer to any standardization of rules. Additionally, Hsu does not provide the possibility of using the design flows of the target technology so that all information as to parametric cells and connectivity (which may be significant for timing analysis purposes) is lost.
Other documents such as US-A-2010/229140, CN-A-101720463, CN-A-101675437, WO-A-2008/031744, and WO-A-2007/147826, which are incorporated by reference, disclose methods applicable within the framework of a strategy as disclosed by Hsu.
In that respect, it is noted that none of these documents properly relates to migration or porting; these documents primarily relate to layouts for shape-level operations.